Power MOSFET active gate drive based on negative feedback mechanism

ABSTRACT

This invention introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide (SiC) and gallium nitride (GaN) semiconductor devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel MOSFET is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. The negative feedback active gate drive (NFAGD) has a simple structure and easy to be realized using a push-pull drive circuit, a drive resistor, an auxiliary MOSFET and an auxiliary capacitor, without involving any additional logical circuits. Functionally, the negative feedback active gate drive (NFAGD) can automatically suppress the induced gate-source voltage and make the gate voltage of the MOSFET stable even during high-speed switching operation without sacrificing the switching speed of the MOSFET.

BACKGROUND OF THE INVENTION 1. Technical Field

The present invention relates to an active gate drive circuit for apower MOSFET based on negative feedback mechanism.

2. Description of Related Art

The emergence of silicon carbide (SiC) and gallium nitride (GaN)semiconductor devices promises to revolutionize next-generation powerelectronics converters [1-4]. Compared with Si devices, SiC and GaNdevices featured with high breakdown electric field, low on-stateresistance, fast switching speed, and high junction temperaturecapability [5, 6]. These characteristics are beneficial for theefficiency, power density, and reliability of power electronicsconverters [7-9]. However, in a practical converter with phase-legconfiguration, the switching transient of one device will impact itscomplementary device, generating the crosstalk phenomenon [4, 10].

The crosstalk phenomenon is characterized by large high-frequency spikesand oscillations on the interfered device's gate voltage. The fastswitching generates high dv/dt and di/dt, which would pass through theMiller capacitance, inducing high-frequency spikes and oscillations onthe gate voltage [11, 12]. Severe spikes and oscillations may lead tofalse triggers and additional switching losses, even lead to shootingthorough [9]. Moreover, overshoot and undershoot of the gate voltage arecritical parameters that influence the switching-induced drift of gatethreshold voltage [13-15]. Crosstalk is the critical element for theswitching behavior of SiC and GaN devices [16-18].

As the interface between power circuits and logic control circuits, gatedrives significantly affect devices' behavior, including the crosstalkphenomenon. However, the conventional gate drive with the fixed driveresistor must tradeoff between switching behaviors, such as switchingspeed, switching loss, switch stresses, and crosstalk suppression[19,20]. Introducing auxiliary passive components for crosstalksuppression also should tradeoff between switching behaviors to obtainsuperior performance [19]. Hence, introducing auxiliary active devicesinto the gate drive circuit, researchers propose various active gatedrives to suppress SiC and GaN Devices crosstalk.

Literature [21] proposed two kinds of active gate drives, namely, GateImpedance Regulation (GIR) and Gate Voltage Control (GVC). GIR predictsthe variation trend of induced gate voltage and controls the auxiliaryactive device preemptively to reduce the gate impedance during theswitching transients. Once its gate impedance becomes small during theswitching transient, most displacement current will be bypassed by thegate loop, resulting in less current that would induce spurious gatevoltage. Thus, crosstalk is mitigated. Similarly, GVC also predicts thevariation trend of induced gate voltage. What is different is that GVCpreemptively charges the gate-source capacitance before the switchingtransients to offset the induced voltage. In the follow-up research,literature [22] proposed the Intelligent Gate Drive (IGD). IGD has agate assist circuit consisting of two auxiliary transistors with twodiodes. By predicting the switching behavior, the assist circuitspreemptively control the gate voltage and gate loop impedances. However,the complex auxiliary logic circuits are needed for detecting theinduced gate voltage, or for predicting the variation trend of theinduced gate voltage, to take preemptive action. However, from theend-users' point of view, additional complexity is added along with thereliability concern due to extra components. Thus, the acceptance andadoption of these advanced gate drive techniques are limited. The fixedoperation cannot self-adaptive following the increase of dv/dt ratingsto ensure real-time control and robustness against parameteruncertainty. Active Miller Clamp (AMC) [11, 12, 23] is a typical activegate drive to attenuate crosstalk and is widely used in commercial gatedrive chips. The gate voltage is detected and the auxiliary clamp deviceis activated preemptively when the gate voltage drops below a thresholdvoltage, a value relative to the turn-off bias voltage. It is thedetected gate voltage that is used to identify the existence ofcrosstalk. However, the detected gate voltage peaks are less than thatacross the internal gate-source terminals because of the relativelylarge internal gate resistance of the devices [21]. Moreover, due to thecircuit propagation delay, the clamping bandwidth is not high enough forthe crosstalk suppression [11, 21]. On the other hand, due to the highswitching speed, the detected gate voltage is interfered with mainly bythe common-source inductance between the drive loop and power loop,which is inevitable in practical situations [21]. AMC technique shows asignificant crosstalk suppression with lower dv/dt ratings; However,some limitations and enlarged disturbance are visible at higher dv/dt,for example, higher than around 20 V/ns in the test bench used in theliterature [11].

With a crosstalk suppression control that features a preemptive action,the existing active gate drive is mainly based on the feed forwardarchitecture [24]. Besides the drive circuit, auxiliary logic circuitsare needed for detecting the induced gate voltage or for predicting thevariation trend of the induced gate voltage to take preemptive action.However, additional complexity is added along with the reliabilityconcern due to extra components. Thus, the acceptance and adoption ofthese advanced gate drive techniques are limited. Furthermore, in theactive gate drive based on the feed forward control architecture, thegate voltage follows the drive's output in an open-loop way. It operatesfixedly, pre-set based on switching behavior prediction. The predictionis not always accurate, especially in a fast switching condition, due todetection deviation, propagation delay and parasitic inductances. Thefixed operation cannot self-adaptive following the increase of dv/dtratings to ensure real-time control and robustness against parameteruncertainty. The active gate drive based on the feedback controlarchitecture naturally attracts the attention of researchers in thisarea.

The negative feedback control is initially implemented in the activegate drive for switching slew rate control [25] in the drive of Si powerdevices. The feedback control is implemented by high bandwidth analogcircuits [26, 27] or digital approaches, such as field-programmable gatearray with high-speed, high-resolution D/A and A/D conversion [28, 29].High dv/dt and di/dt can result in crosstalk phenomenon with gateglitch, false-triggering, and other detrimental effects during switchingtransients. Unlike the design criterion of active gate drivers for Sipower devices, crosstalk suppression for gate voltage stability iscritical for SiC and GaN devices because of their low threshold voltageand considerable internal gate resistance. Several researchers haveinvestigated the SiC or GaN based switching transition negative feedbackcontrol by either electrical approach [30] or optical approach [31, 32]but with relatively slow switching speed. Also, limited feedback controlworks focus on crosstalk suppression.

The implementation of negative feedback control in fast switching SiCand GaN devices for crosstalk suppression is challenging. Firstly,considering the switching time for SiC and GaN devices is as short astens of nanoseconds, the propagation delay of the feedback control is aconcern since it may be comparable, even longer than the switching time.Secondly, fast switching is always associated with parasitic ringing sothat sensors that attempt to identify different switching subintervalseasily interfere, resulting in improper operation. Generally, a highswitching speed is desired due to the lower switching loss. However,coordinated optimization of gate voltage stability and switching speedis challenging.

This paper proposes a negative feedback active gate drive (NFAGD)employing one auxiliary P-channel MOSFET and one auxiliary capacitortogether with the drive resistor for fast switching and crosstalksuppression base on the negative feedback control mechanism. Thecombined operation mechanism based on negative feedback control in thedrive-semiconductor system is given to show the basic operationprinciple of the proposed gate drive. This paper then shows a designreference and experimental test results with commercial 1200V SiCMOSFETs to demonstrate the validity and effectiveness of the proposedmethodology.

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SUMMARY OF THE INVENTION

The technical issue to be solved by the present invention is to providea power MOSFET gate drive based on negative feedback mechanism, whichcan automatically suppress the induced gate voltage, or the so-calledcrosstalk, without sacrificing the switching speed and withoutincreasing circuit complexity of a MOSFET.

The objective of the present invention is achieved by providing a MOSFETgate drive based on the negative feedback mechanism. The gate drive isused to connect the drive signal to enable or disable the switchingaction of the controlled MOSFET, comprising: an auxiliary MOSFET, beinga P-channel MOSFET, and having its source connected to the gate of thecontrolled MOSFET for creating a negative feedback regulating mechanism,the auxiliary MOSFET having its drain connected to a drive voltage; thedrive voltage is the output voltage of a push-pull drive circuit(usually realized by a conventional gate drive chip along with its powersupplies) that has been filtered by a passive network which comprises adrive resistor R and an auxiliary capacitor C.

Moreover, the circuit further comprises:

(1) a first node, a second node, and a third node;

(2) a push-pull drive circuit, for providing a driving current to drivethe controlled MOSFET, the drive signal being connected to theconventional gate drive chip or to a totem-pole circuit, forming thepush-pull drive circuit, and the push-pull drive circuit and the thirdnode being connected in series;

(3) a drive resistor R, having one end connected in series with thepush-pull drive circuit, and having an opposite end connected to thefirst node, for limiting a charging/discharging current applied to anauxiliary capacitor C by the push-pull drive circuit;

(4) a voltage difference between the first node and a source of thecontrolled MOSFET being the drive voltage;

(5) an auxiliary capacitor C, having one end connected to the first nodeand having an opposite end connected to the source of the controlledMOSFET through the third node, so as to work with the drive resistor Rto form the passive network for regulating a switching speed of thecontrolled MOSFET;

(6) the drain and the gate of the auxiliary MOSFET connect in serieswith the drive resistor R through the second node, the source of theauxiliary MOSFET is connected to the gate of the controlled MOSFET forcreating the negative-feedback regulating mechanism.

Further, the push-pull drive circuit comprises: a conventional gatedrive chip; an on-bias voltage V_(CC) and an off-bias voltage V_(EE).The conventional gate drive chip having a positive supply terminal (theoutput side of isolation) connected to the positive pole of the on-biasvoltage V_(CC), the conventional gate drive chip having a positivesupply terminal (the output side of isolation) connected to the negativepole of the off-bias voltage V_(EE), the conventional gate drive chiphaving a drive output terminal connected to one end of the driveresistor R and having a drive input terminal connected to the drivesignal; and a negative pole of the on-bias voltage V_(CC) and a positivepole of the off-bias voltage V_(EE) both being connected to the thirdnode. The conventional gate drive chip has a maximum permissible outputcurrent not smaller than (V_(CC)−V_(EE))/R_(g), where R_(g) is theinternal gate resistance of the controlled MOSFET.

Further, the auxiliary MOSFET has a drain-source breakdown voltage notsmaller than V_(CC)−V_(EE), and has a maximum permissible continuousdrain current not smaller than (V_(CC)−V_(EE))/R_(g).

The present invention has the following advantages. The negativefeedback active gate drive (NFAGD) has a simple structure and easy to berealized using a conventional gate drive chip, a drive resistor, anauxiliary MOSFET and an auxiliary capacitor, without involving anyadditional logical circuits. Functionally, the negative feedback activegate drive (NFAGD) can automatically suppress the induced gate-sourcevoltage and make the gate voltage of the MOSFET stable even duringhigh-speed switching operation without sacrificing the switching speedof the MOSFET. In subsequent embodiments, compared to conventionalpassive suppression approaches, the negative feedback active gate drive(NFAGD) provides greater suppression of gate-source voltage spikes andoscillation. It can suppress the crosstalk without influencing theswitching speed, thus enables coordinated optimization of gate voltagestability and switching behavior.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be best understood by reference to the followingdetailed description of illustrative embodiments when read inconjunction with the accompanying drawings:

FIG. 1 is a circuit diagram of a negative feedback active gate drive(NFAGD) of the present invention;

FIG. 2 is a block diagram showing control of the negative feedbackactive gate drive (NFAGD) of the present invention;

FIG. 3 depicts a negative feedback active gate drive in a phase-legstructure according to one embodiment of the present invention;

FIG. 4a is a schematic waveform diagram during the turning on process ofQ_(H) using the negative feedback active gate drive;

FIG. 4b is a schematic waveform diagram during the turning off processof Q_(H) using the negative feedback active gate drive;

FIG. 5a is a diagram of an experimental circuit with the conventionalgate drive without suppression for comparison with one embodiment of thepresent invention;

FIG. 5b is a diagram of an experimental circuit with the conventionalgate drive that used passive suppression for comparison with oneembodiment of the present invention;

FIG. 5c is a diagram of an experimental circuit with one embodiment ofthe present invention;

FIG. 6a is the experimental waveform of one switching cycle of anexperimental circuit with the conventional gate drive withoutsuppression;

FIG. 6b is the enlarged rising edge of v_(DS2) of an experimentalcircuit with the conventional gate drive without suppression;

FIG. 6c is the enlarged falling edge of v_(DS2) of an experimentalcircuit with the conventional gate drive without suppression;

FIG. 7a is the experimental waveform of one switching cycle of anexperimental circuit with the conventional gate drive that used passivesuppression;

FIG. 7b is the enlarged rising edge of v_(DS2) of an experimentalcircuit with the conventional gate drive that used passive suppression;

FIG. 7c is the enlarged falling edge of v_(DS2) of an experimentalcircuit with the conventional gate drive that used passive suppression;

FIG. 8a is the experimental waveform of one switching cycle of anexperimental circuit with one embodiment of the present invention;

FIG. 8b is the enlarged rising edge of v_(DS2) of an experimentalcircuit with one embodiment of the present invention;

FIG. 8c is the enlarged falling edge of v_(DS2) of an experimentalcircuit with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

One mode for implementing the present invention is now described.

As shown in FIG. 1, a negative feedback active gate drive (NFAGD) isused to drive a MOSFET Q_(N). The output of a conventional gate MOSFETdrive is connected to a network, constituted by the drive resistor R andthe auxiliary capacitor C. The output of the RC network is also regardedas the drive reference vGS*. It then goes to the gate and source ofcontrolled MOSFET through the auxiliary MOSFET. For building thenegative feedback, the controlled MOSFET and auxiliary MOSFET shouldhave a complementary channel characteristic. Usually, the controlledMOSFET is N-channel. Hence the auxiliary MOSFET is P-channel. Hereafter,this invention denotes the controlled MOSFET and the auxiliary MOSFET asQN and QP. The RC network is responsible for tuning the speed ofswitching. The gate voltage vGS would follow the drive reference vGS*,owing to the negative feedback control. Hence the speed of gate voltagevGS is similar to that of the drive reference vGS*.

FIG. 2 illustrates the negative feedback regulating mechanism possessedby the circuit of the present invention. The analysis is based on twosimplifications to explain the mathematical nature of NFAGD forunderstanding. Firstly, the transconductance gain of the auxiliaryMOSFET Q_(P) is treated as a non-time-varying constant g_(m). Thereverse transconductance gain of the parasitic body diode (the slope ofthe output characteristic curve) is also expressed by g_(m). Secondly,the reverse conducting threshold voltage of the auxiliary MOSFET Q_(P)is equal to its forward conducting threshold voltage, and both aredenoted V_(th). The close-loop transfer function of the NFAGD can bederived from the block diagram shown in FIG. 1, given as:

$\begin{matrix}{{\Phi(s)} = {\frac{v_{GS}(s)}{v_{GS}*(s)} = \frac{G(s)}{1 + {G(s)}}}} & (1)\end{matrix}$

Where G(s) is the open-loop transfer function of NFAGD, given as:

$\begin{matrix}{{{G(s)} = {{g_{m}\left( {\frac{1}{sC_{ss}} + R_{g}} \right)} = \frac{g_{m}}{C_{iss}}}}\frac{{{sR}_{g}C_{iss}} + 1}{s}} & (2)\end{matrix}$

According to the system dynamic theory, the NFAGD is a unity-feedbacktype 1 control system. The open-loop gain is g_(m)/C_(iss). Staticvelocity error constant can be expressed as:

$\begin{matrix}{K_{v} = {{\lim\limits_{s\rightarrow 0}{s{G(s)}}} = \frac{g_{m}}{C_{iss}}}} & (3)\end{matrix}$

In general, the input capacitance of controlled MOSFET (C_(iss)) isabout several nano-farads. Simultaneously, the transconductance gain ofthe auxiliary MOSFET (g_(m)) is far larger than 1 Siemens, thereforeunder the international system of units, we can get g_(m)>>C_(iss), sothe static velocity error constant K_(v) is large enough. Therefore,when the gate voltage v_(GS) tracks the ramping drive reference v_(GS)*,the deviation between them is small enough and does not affect theturn-on and turn-off of the controlled SiC MOSFET following thedesigner's request. Moreover, due to the large static velocity errorconstant K_(v), the suppression ratio of the disturbance n(s) is largeenough to attenuate the induced spikes and oscillations on gate voltagev_(GS)(s).

As shown in FIG. 3, the depicted embodiment shows a negative feedbackactive gate drive (NFAGD) used in a phase-leg structure. To facilitatethe reader to understand the working principle, it demonstrates thecontrolled SiC MOSFETs (Q_(H) and O_(L)) with the junction capacitors,representing the devices' dynamic characteristics. The meaning of eachsymbol in FIG. 3 is similar to that shown in FIG. 1. Only to distinguishupper and lower devices, adding marks “1” and “2” respectively, or marks“L” and “H”. R₁ and R₂ represent the drive resistor of the upper andlower devices, respectively. C₁ and C₂ represent the auxiliary capacitorof the upper and lower devices, respectively. Q_(P1) and Q_(P2)represent the auxiliary MOSFET of the upper and lower devices,respectively. As the active device in the phase-leg, Q_(H) is turning onand off under the control of signal S₁. Q_(L) is the non-active devicein the phase-leg, and its control signal S₂ steady at a low level tokeep the channel of Q_(L) turning off and only its parasitic body diodeis used for freewheeling.

The miller capacitances C_(gdH) and C_(gdL) of the controlled MOSFETsdecrease with their drain voltage. For understanding, the analysisintroduces the piecewise linearization curve to approximate the actualcurve for simplification. When the drain voltage is larger than the gatevoltage, the value of miller capacitance is C_(gd1). When the drainvoltage is less than the gate voltage, the value of miller capacitanceis C_(gd2). The output current at the midpoint of the phase-leg isapproximately constant during the switching process and represented byI_(L).

FIG. 4a and FIG. 4b show theoretical waveforms of the circuit of FIG. 3in the dynamic processes of turning on and off Q_(H), with the initialmoments being the moment when S₁ changes from the low level to the highlevel and the moment when S₁ changes from the high level to the lowlevel, respectively. The two dynamic processes each have 4 modes, whichwill be detailed below:

Turning on Q_(H), as shown in FIG. 4a

Turn-on mode 1: during the turn-on delay time t_(d(on)). At t=0 timepoint, S₁ changes from low level to high level. The driver IC charges C₁through R₁. Hence, the drive voltage v_(GS1)* increases, graduallyrising from V_(EE1) to V_(CC1). Because of the negative feedbackmechanism, the gate voltage v_(GS1) tracks v_(GS1)* and also increasesgradually. It should be noticed that, as mentioned above, the NFAGDsystem is a unity-feedback type 1 control system. There is some error inthe tracking of the ramping drive reference v_(GS1)*. The tracking errorwill not affect the regular operation due to the large value of thestatic velocity error constant. In this mode, since v_(GS1) is stillless than the threshold voltage V_(GS,th), the channel of Q_(H) is inthe off-state, i_(D1)=0 can be got. V_(DS1) stands still at V_(DC), andthis mode ends when v_(GS1) reaches V_(GS,th).

Turn-on mode 2: during the current rise time t_(ri), V_(GS1) starts fromthe threshold voltage V_(GS,th), and rises to V_(GS,IL), which indicatesthe value of v_(GS1) that can maintain channel current at I_(L). V_(DS1)stands still at V_(DC). The current i_(D1) rises from 0 to I_(L). Duringthis process, due to the decrease of the passive device's currenti_(D2), the gate voltage of Q_(L)v_(GS2) increases slightly but notlarge enough to trigger the conduction of Q_(P2). The mode ends at themoment when the current i_(D1) rises to I_(L).

Turn-on mode 3: during the first voltage decrease time t_(fv1), the gatevoltage of Q_(H)(v_(GS1)) still tracks v_(GS1)* as the negative feedbackcontrols. The drive circuit continues to charge C_(gdH) and C_(gsH)through the active control of auxiliary MOSFET. This charging currentweakens the influence of the miller effect on the gate voltage. Themiller platform appears for a very short time, which is not apparent inthe waveform. In this mode, v_(DS1) falls from V_(DC). Since the drainvoltage is still larger than the gate voltage, the value of C_(gdH) isstill relatively small (C_(gd1)). Therefore v_(DS1) falls at arelatively fast rate at this stage. Q_(L)'s drain voltage (v_(DS2))rises rapidly, which induces Q_(L)'s gate voltage (v_(GS2)) risessignificantly. Due to the negative feedback mechanism, when the electricpotential of S_(P2) is higher than that of D_(P2) and the electricpotential difference exceeds the threshold voltage V_(th), leading tothe conduct of Q_(P2). Then the drive IC discharges the inputcapacitance of Q_(L)(C_(issL)) through the channel of Q_(P2). Hence theQ_(L)'s gate voltage v_(GS2) decreases, returning to V_(EE2) and thedisturbance is suppressed. This mode ends when v_(DS1) falls to a valueequal to v_(GS1).

Turn-on mode 4: during the second voltage decrease time t_(fv2), due tothe negative feedback mechanism, the gate voltage v_(GS1) still risesalong with v_(GS1)*, instead of remaining unchanged at V_(GS,IL).v_(DS1) continues to fall. Since the drain voltage is less than the gatevoltage, the value of C_(gdH) is relatively large (C_(gd2)), and thefalling rate of v_(DS1) in this stage is relatively slow. This mode endswhen v_(DS1) descends to V_(DS(on)).

After the turn-on mode 4, due to the negative feedback mechanism, thegate voltage v_(GS1) still rises to the bias voltage V_(CC1), trackingits drive reference signal v_(GS1)*. At this moment, the turn-on processis finally completed.

Turning off Q_(H), as shown in FIG. 4b

Turn-off mode 1: during the turn-off delay time t_(d(off)). At t=0 timepoint, S₁ changes from high level to low level. The driver IC dischargesC₁ through R₁. Hence, the drive voltage v_(GS1)* decreases, graduallyfalling from V_(CC1) to V_(EE1). Because of the negative feedbackmechanism, the gate voltage v_(GS1) tracks v_(GS1)* and also decreasesgradually. It should be noticed that, as mentioned above, the NFAGDsystem is a unity-feedback type 1 control system. There is some error inthe tracking of the ramping drive reference v_(GS1)*. The tracking errorwill not affect the regular operation due to the large value of thestatic velocity error constant. In this mode, since v_(GS1) is stilllarger than the threshold voltage V_(GS,th), the channel of Q_(H) is inthe on-state, i_(D1)=I_(L) can be got. V_(DS1) stands still atV_(DS(on)), and this mode ends when v_(GS1) reaches V_(GS,IL).

Turn-off mode 2: during the first voltage rise time t_(rv1), the gatevoltage of Q_(H)(v_(GS1)) still tracks v_(GS1)* as the negative feedbackcontrols. The drive circuit continues to discharge C_(gdH) and C_(gsH)through the active control of auxiliary MOSFET. This charging currentweakens the influence of the miller effect on the gate voltage. Themiller platform appears for a very short time, which is not apparent inthe waveform. In this mode, v_(DS1) rises from V_(DS(on)). Since thedrain voltage is still less than the gate voltage, the value of C_(gdH)is still relatively large (C_(gd2)). Therefore v_(DS1) rises at arelatively slow rate at this stage. This mode ends when v_(DS1) rises toa value equal to v_(GS1).

Turn-off mode 3: during the second voltage rise time t_(rv2), due to thenegative feedback mechanism, the gate voltage v_(GS1) still decreasesalong with v_(GS1)*. v_(DS1) continues to increase. Since the drainvoltage is larger than the gate voltage, the value of C_(gdH) isrelatively small (C_(gd1)), and the rising rate of v_(DS1) in this stageis relatively fast. Q_(L)'s drain voltage (v_(DS2)) falls rapidly, whichinduces Q_(L)'s gate voltage (v_(GS2)) to fall significantly. Due to thenegative feedback mechanism, when the electric potential of D_(P2) ishigher than that of S_(P2) and the electric potential difference exceedsthe threshold voltage of the parasitic body diode of Q_(P2). The driveIC charges the input capacitance of Q_(L) (C_(issL)) through theparasitic body diode of Q_(P2). Hence the Q_(L)'s gate voltage v_(GS2)increases, returning to V_(EE2) and the disturbance is suppressed. Thismode ends when v_(DS1) rises to a value equal to V_(DC).

Turn-off mode 4: during the current fall time t_(fi), due to thenegative feedback mechanism, the gate voltage v_(GS1) still falls alongwith v_(GS1)* until it reaches V_(GS,th). In this mode, v_(DS1) remainsunchanged in V_(DC). This mode ends when i_(D1) falls to 0.

After the turn-off mode 4, due to the negative feedback mechanism, thegate voltage v_(GS1) still falls to the bias voltage V_(EE1), trackingits drive reference signal v_(GS1)*. At this moment, the turn-offprocess is finally completed.

The exemplary parameters for disclosed NFAGD are designed with thefollowing considerations.

To better understand the combined operation mechanism based on negativefeedback control in the drive-semiconductor system, this paper wouldalso show the design principle of the negative feedback active gatedrive (NFAGD).

A. Selection Principle for the Controlled SiC MOSFET

When adopting the NFAGD, the controlled SiC MOSFET should be determinedaccording to the converters' operation condition, like the conventionalsemiconductor power device derived by other drive circuits. Generally,the SiC MOSFET is selected by the maximum working voltage and current ofthe device to ensure a safe operating area. For example, in this paper'sexperiment, the 1200V SiC MOSFET IMZ120R030M1H with highcommercialization degree in high power conditions is selected as thecontrolled SiC MOSFET demonstrate and verify the technical feasibilityof the proposed method. The maximum drain-source voltage is 1200V, themaximum drain current 56 A, and the internal gate resistance is 3Ω.

B. Drive IC Selection and Peripheral Circuit Design Principles

The proposed NFAGD has the effect of stabilizing the gate voltage,attenuating the interference effects from the pulse voltage and pulsecurrent. However, it does not eliminate the gate instability problemonce for all. Considering the low threshold voltage of the controlledSiC MOSFET (approximately 2˜4V), the negative turn-off bias voltage iscritical. While the turn-on bias voltage usually relates to the on-stateresistance, whose design should refer to a typical suggestion from thedatasheet. This paper recommends the turn-on bias voltage V_(CC)=15˜22Vand turn-off bias voltage V_(EE)=−5˜0V. Based on the aboveconsiderations, the bias voltages V_(CC)=20V and V_(EE)=−5V are adoptedin the subsequent design.

This paper recommends the drive IC's isolation part has a common modetransient immunity CMTI≥100V/ns (within the full temperature range). Thedrive IC output current should be no less than (V_(CC)−V_(EE))/R_(g),where R_(g) is the internal gate resistance of the controlled SiCMOSFET. For example, the selected controlled SiC MOSFET (IMZ120R030M1H)internal gate resistance R_(g)=3Ω, the bias voltages V_(CC)=20V andV_(EE)=−5V is adopted. In one implementation, the drive chip used is1ED3124MU12H with an output current up to 14 A.

C. Selection Principle for the Auxiliary MOSFET

The auxiliary MOSFET is the P-channel MOSFET with a relatively lowvoltage rating in the drive circuit without flowing through a largecurrent and endues large voltage. Meanwhile, to ensure the controlaccuracy, the transconductance gain (g_(m)) of the auxiliary MOSFETshould be larger than 1 Siemens. The auxiliary MOSFET bears a certaincurrent and voltage during the switching transients of the controlledSiC MOSFET. Hence, the auxiliary MOSFET's maximum current and voltageshould be designed according to the bias voltages V_(CC) and V_(EE).

The auxiliary MOSFET is subjected to a certain level of voltage andcurrent during the switching transients of the controlled SiC MOSFET.Hence the maximum voltage and current of the auxiliary MOSFET should bedesigned according to the bias voltages V_(CC) and V_(EE). We recommendthe maximum voltage should be no less than V_(CC)−V_(EE), the maximumcurrent should be no less than (V_(CC)−V_(EE))/R_(g). Based on the aboveanalysis, FDS9435A is used as the P-channel auxiliary MOSFET, with adrain-source breakdown voltage of 30(V), a maximum permissiblecontinuous drain current of 25 (A), and a transconductance gain of10(S).

D. Design Principles for Auxiliary Capacitors and Drive Resistors

The auxiliary capacitor and the drive resistor (i.e., C and R in FIG. 1)connected to the output end of the push-pull drive circuit jointlydetermines the rising/falling speed of v_(GS). Generally, the inputcapacitance of the controlled MOSFET is about the nF level, and thetransconductance gain of the auxiliary MOSFET is much greater than 1(S).Therefore, the open-loop gain of the gate negative feedback activeMOSFET-driving circuit is large enough. When v_(GS) tracks theramp-rising (falling) v_(GS)*, the deviation between the two is quitesmall, and v_(GS)* and v_(GS) have an approximately equal rising/fallingspeed. The auxiliary capacitor C also provides the function ofdecoupling, for shortening the “electrical circumference” of the loopcomposed of the output end of the push-pull drive circuit and thegates-sources of the auxiliary MOSFET and the controlled MOSFET. Therecommended auxiliary capacitor Cat a site of the power loop of thephase-leg circuit having an undamped self-sustained oscillationfrequency has an impedance not greater than 0.2Ω, that is:

$\left. {\frac{\sqrt{L_{o}C_{oss}}}{C} \leq {0.2}}\Rightarrow{C \geq {5\sqrt{L_{o}C_{oss}}}} \right.$

In this embodiment, the controlled MOSFET (IMZ120R030M1H) has an outputcapacitance of C_(oss)=116 pF, and the stray inductance L_(o) of thepower loop is estimated to be 50 nH. According to the foregoingequation, the auxiliary capacitor C should not be smaller than 12 nF.Engineeringly, the selected auxiliary capacitor C=20 nF so as to ensurethat the impedance at the site of the power loop having the undampedself-sustained oscillation frequency has an impedance that is smallenough.

After the auxiliary capacitor C is selected, design of the driveresistor R can be started. The product of the drive resistor R and theauxiliary capacitor C is τ=RC, being the charging/discharging timeconstant of the resistance-capacitance circuit. The charging/dischargingtime constant τ is inversely proportional to the rising/descending slopeof the gate-source voltage. In other words, the larger thecharging/discharging time constant τ is, the slower the gate-sourcevoltage rises/falls, in turn leading to slower switching speed of thecontrolled MOSFET. That means if a higher switching speed of thecontrolled MOSFET is desired, such as when it is needed to reduce lossand enhance efficiency, a smaller charging/discharging time constant τis preferable. However, additional functional concerns of the driveresistor R are current limits and protection it provides for thepush-pull drive circuit. At the beginning of the switching operation,the current of the push-pull drive circuit charging/discharging theauxiliary capacitor C through the drive resistor R reaches the peak(V_(CC)−V_(EE))/R. For making the most use of the loading budget of thedrive chip selected to the present embodiment and realizing a relativelyfast switching speed of the MOSFET, in the present embodiment, thecharging/discharging current peak (V_(CC)−V_(EE))/R is such designedthat it is 70% of the peak output current of the drive chip. Inparticular, the 70% of the maximum output current of maximum outputcurrent of 1ED3124MU12H with the on voltage V_(CC)=20V and the offvoltage V_(EE)=−5V is about 10 A. Therefore, the drive resistor R=2.5Ω,and the corresponding charging/discharging time constant τ=50 nS. It isto be noted that the described design of the drive resistor R isillustrative, and in various industrial applications, the drive resistormay be flexibly designed otherwise and adapted to practical needs interms of efficiency, loss, and electromagnetic compatibility, togetherwith the selection of the auxiliary capacitor.

It is to be noted that the described design of the drive resistor R isillustrative, and in various industrial applications, the drive resistormay be flexibly designed otherwise and adapted to practical needs interms of efficiency, loss, and electromagnetic compatibility, togetherwith the selection of the auxiliary capacitor.

FIG. 5a shows a diagram of an experimental circuit with the conventionalgate drive without suppression for comparison with one embodiment of thepresent invention; FIG. 5b shows a diagram of an experimental circuitwith the conventional gate drive that used passive suppression forcomparison with one embodiment of the present invention; FIG. 5c shows adiagram of an experimental circuit with one embodiment of the presentinvention;

Each of these was provided with a drive pulse to drive the active MOSFETQ_(H) and was provided with a negative voltage bias to turn off thepassive MOSFET Q_(L). In the embodiment, three instances were set up tocompare how the gate-source voltage v_(GS2) of the passive tube Q_(L)could be interfered for demonstrating the effectiveness of the NFAGD instabilizing the gate-source voltage.

FIG. 6a through FIG. 6c exhibit experimental waveforms of anexperimental circuit with the conventional gate drive withoutsuppression for comparison with one embodiment of the present invention.The drivers for the active tube Q_(H) and the passive tube Q_(L) wereonly each provided with a drive resistor. The corresponding driveresistors were both of 10Ω. As shown in FIG. 6a , the gate-sourcevoltage v_(GS2) of the passive tube Q_(L) was interfered and showedobvious oscillation, with a forward interference magnitude up to 7.9V,and a negative interference magnitude up to 7V As shown in FIG. 6b , inthe process where the drain-source voltage v_(DS2) of the passive tubeQ_(L) rose, the rising slope of 100V-800V was about 43.7V/ns. As shownin FIG. 6c , in the process where the drain-source voltage v_(DS2) ofthe passive tube Q_(L) fell, the descending slope of 800V-100V was about51.25V/ns. It is clear that the drain-source voltage v_(DS2) of thepassive tube Q_(L) rose and fell faster, making the gate-source voltagev_(GS2) of Q_(L) obviously instable.

FIG. 7a through 7c show experimental waveforms of an experimentalcircuit with the conventional gate drive that used passive suppressionfor comparison with one embodiment of the present invention. The drivingcircuit for the active tube Q_(H) and for the passive tube Q_(L) wasrealized using gate-source shunt auxiliary capacitors. The driveresistors R₁, R₂ were 10Ω, and the gate-source shunt auxiliarycapacitors C_(a1), C_(a2) were 2 nF. As shown in FIG. 7a , theinterference-induced oscillation at the gate-source voltage v_(GS2) ofthe passive tube Q_(L) had a certain mitigate, with the forwardinterference magnitude being about 4V, and the negative interferencemagnitude being about 4V, too. As shown in FIG. 7b , in the processwhere the drain-source voltage v_(DS2) of the passive tube Q_(L) rose,the rising slope of 100V-800V was about 42.5V/ns. As shown in FIG. 7c ,in the process where the drain-source voltage v_(DS2) of the passivetube Q_(L) fell, the descending slope of 800V-100V was about 9.6V/ns.Compared to the switching speed of the embodiment as shown in FIG. 6athrough FIG. 6c significant decrease can be observed. It is thus clearthat while passive gate oscillation suppression using gate-source shuntauxiliary capacitors effectively suppressed gate-source oscillation, theswitching speed was sacrificed as a cost.

FIG. 8a through FIG. 8c show experimental waveforms of one embodiment ofthe present invention using the NFAGD. The driving circuits for theactive tube Q_(H) and for the passive tube Q_(L) were both realizedusing NFAGD. As shown in FIG. 8a , interference-induced oscillation atthe gate-source voltage v_(GS2) of the passive tube Q_(L) was mitigatedmore significantly, with the forward interference magnitude being about3V and the negative interference magnitude being about 3V, too. As shownin FIG. 8b , in the process where the drain-source voltage v_(DS2) ofthe passive tube Q_(L) rose, the rising slope of 100V-800V was about50V/ns. As shown in FIG. 8c , in the process where the drain-sourcevoltage v_(DS2) of the passive tube Q_(L) fell, the descending slope of800V-100V was about 50V/ns. Compared to the passive suppression approachof the embodiment shown in FIG. 7a through FIG. 7c , the gate negativefeedback active suppression circuit of the present invention providedmore significant suppression of oscillation for the gate-source voltage,without sacrificing the switching speed. With the auxiliary capacitor(20 nF), compared to the switching speed of the embodiment as shown inFIG. 6a through FIG. 6c , the present invention improved the switchingspeed definitely.

An alternative mode for implementing the present invention will be givenbelow.

As shown in FIG. 1, a negative feedback active gate drive (NFAGD), forconnecting a drive signal to turn on and off a power MOSFET, i.e. thecontrolled MOSFET, comprises a push-pull drive circuit, a driveresistor, an auxiliary capacitor, and an auxiliary MOSFET.

The push-pull drive circuit, for generating a drive voltage v_(GS)* thatcontrols a wide bandgap semiconductor device such as a SiC MOSFET or aGallium Nitride Transistor. In particular, it provides a driving currentto drive the controlled MOSFET. The drive signal is connected to thepush-pull drive circuit (usually composed by the conventional gate drivechip and its power supplies), and the push-pull drive circuit and thethird node are connected in series.

The drive resistor R has its one end connected in series with thepush-pull drive circuit and an opposite end connected to the first node,for limiting a charging/discharging current applied to an auxiliarycapacitor C by the push-pull drive circuit, thereby providing currentlimits and protection. A voltage difference between the first node and asource of the controlled MOSFET is the drive voltage.

The auxiliary capacitor C has one end connected to the first node, andan opposite end connected to the source S of the controlled MOSFETthrough the third node, so as to work with the drive resistor R to formthe passive network for regulating a switching speed of the controlledMOSFET.

The auxiliary MOSFET is a P-channel MOSFET. Its source connected to thegate of the controlled MOSFET for creating a negative-feedbackregulating mechanism, and its drain is connected to a drive voltage. Thedrive voltage is a voltage of a push-pull drive circuit that has beenfiltered by a passive network. The drain D_(p) and the gate G_(p) of theP-channel MOSFET are connected in series with the drive resistor Rthrough the second node. The source S_(p) of the P-channel MOSFET isconnected to the gate G of the controlled MOSFET, for creating anegative-feedback regulating mechanism, thereby realizing self-stabilityof the gate voltage.

The push-pull drive circuit usually comprises a conventional gate drivechip and its power supplies, denoted as an on-bias voltage V_(CC), andan off-bias voltage V_(EE). The conventional gate drive chip has anoutput power positive terminal connected to the positive pole of theon-bias voltage V_(CC). The conventional gate drive chip has an outputpower negative terminal connected to the negative pole of the off-biasvoltage V_(EE). The conventional gate drive chip has a drive outputterminal connected to one end of the drive resistor R and has a driveinput terminal connected to the drive signal. The negative pole of theon-bias voltage V_(CC) and the positive pole of the off-bias voltageV_(EE) are both connected to the third node. The push-pull drive circuitcan be simply realized using a conventional gate drive chip or a totempole circuit for MOSFETs. The V_(CC) is the on-bias voltage, and therecommended on-bias voltage value is 18˜22V. The V_(EE) is the off-biasvoltage, and the recommended off-bias voltage value is −2.5˜−5V Therecommended common-mode transient immunity (CMTI) for the drive chip is≥100V/ns (over the full temperature range). In terms of drivingcapability, the chip output current should not be smaller than(V_(CC)−V_(EE))/R_(g), where R_(g) is the gate internal gate resistanceof the controlled MOSFET.

Since the P-channel MOSFET has to bear certain levels of voltages andcurrents when the controlled MOSFET is switching, for ensuring itsworking safety, the levels of the voltages and currents of the auxiliaryMOSFET have to be determined according to the on-bias voltage V_(CC) andthe off-bias voltage V_(EE) of the designed push-pull drive circuit, andthe gate properties of the controlled MOSFET. The recommendeddrain-source breakdown voltage is not smaller than V_(CC)−V_(EE), andthe recommended maximum permissible continuous drain current is notsmaller than (V_(CC)−V_(EE))/R_(g). Meanwhile, for ensuring the controlprecision, the transconductance gain of the P-channel auxiliary MOSFETshould be much greater than 1(S).

Functionally, the auxiliary capacitor C not only regulates the switchingspeed of the controlled MOSFET, but also helps to minimize the area ofthe loop formed by the push-pull drive circuit, the auxiliary MOSFET,and the gate and source of the controlled MOSFET, realizinghigh-frequency decoupling of the drive loop.

The present invention has been described with reference to the preferredembodiments and it is understood that the embodiments are not intendedto limit the scope of the present invention. Moreover, as the contentsdisclosed herein should be readily understood and can be implemented bya person skilled in the art, all equivalent changes or modificationswhich do not depart from the concept of the present invention should beencompassed by the appended claims.

What is claimed is:
 1. A power MOSFET gate drive based on negativefeedback mechanism, for connecting a drive signal to turn on and off acontrolled MOSFET, comprising: an auxiliary MOSFET, being a P-channelMOSFET, and having its source connected to a gate of the controlledMOSFET for creating a negative-feedback regulating mechanism, theauxiliary MOSFET having its drain connected to a drive voltage; thedrive voltage being a voltage of a drive chip that has been filtered bya passive network; a first node, a second node, and a third node; apush-pull drive circuit, for providing a driving current to drive thecontrolled MOSFET, the drive signal being connected to the push-pulldrive circuit, and the push-pull drive circuit and the third node beingconnected in series; and a drive resistor R, having one end connected inseries with the push-pull drive circuit, and having an opposite endconnected to the first node, for limiting a charging/discharging currentapplied to an auxiliary capacitor C by the push-pull drive circuit, anda voltage difference between the first node and a source of thecontrolled MOSFET being the drive voltage; the auxiliary capacitor Chaving one end connected to the first node and having an opposite endconnected to the source of the controlled MOSFET through the third node,so as to work with the drive resistor R to form the passive network forregulating a switching speed of the controlled MOSFET; wherein the drainand the gate of the auxiliary MOSFET connect in series with the driveresistor R through the second node, and the source of the auxiliaryMOSFET is connected to the gate of the controlled MOSFET for creatingthe negative-feedback regulating mechanism.
 2. The power MOSFET gatedrive based on negative feedback mechanism of claim 1, wherein thepush-pull drive circuit comprises a MOSFET gate drive chip, an on-biasvoltage V_(CC) and an off-bias voltage V_(EE); the MOSFET gate drivechip having a positive supply terminal connected to a positive pole ofthe on-bias voltage V_(CC), the MOSFET gate drive chip having a negativesupply terminal connected to a negative pole of the off-bias voltageV_(EE), the MOSFET gate drive chip having a drive output terminalconnected to one end of the drive resistor R and having a drive inputterminal connected to the drive signal; and a negative pole of theon-bias voltage V_(CC) and a positive pole of the off-bias voltageV_(EE) both being connected to the third node, whereby in terms ofdriving capability, a permissible output current of the MOSFET drivechip should not be smaller than (V_(CC)−V_(EE))/R_(g).
 3. The powerMOSFET gate drive based on negative feedback mechanism of claim 1,wherein the auxiliary MOSFET has a drain-source breakdown voltage notsmaller than V_(CC)−V_(EE), and has a maximum permissible continuousdrain current not smaller than (V_(CC)−V_(EE))/R_(g).